1. Field of Invention
The present invention relates to a mask read only memory cell. More particularly, the present invention relates to a method for forming a multi-level mask read only memory and a multi-level mask read only memory.
2. Description of Related Art
Generally, the mask read only memory (ROM) can be divided as NOR type mask ROM and NAND type mask ROM. Although the NOR type mask ROM usually affords larger cell currents, the fabrication processes are more complicated. On the other hand, the NAND type Mask ROM can provide dense cell sizes and employ fabrication processes compatible with the standard Logic processes.
In general, the structure of the mask ROM includes a plurality of bit lines and a plurality of polysilicon word lines bridging over the bit lines. Channel regions of the memory cells are beneath the word lines and between two neighboring bit lines. The mask ROM cells can be programmed to store data. For the NAND type mask ROM cell programming, the stored logic data is either “0” or “1” depending on whether the ions are implanted into the channel regions or not. Such implantation process, implanting ions or dopants into the specific channel regions, is so called code implantation process.
The NAND type ROM memory consists of series MOS transistors, including depletion mode MOS transistors and enhancement mode MOS transistors. Providing the intrinsic MOS transistor is the enhancement mode NMOS transistor and the threshold voltage is positive, the ROM code implantation implants impurities into the channel region of the depletion mode NMOS transistor and changes its threshold voltage to be negative. In general, for the conventional mask ROM, each memory cell can be programmed to store only one bit data (i.e. either “0” or “1”) at one time.
However, as high performance ROM memory is highly demanded and the chip size keeps decreasing, it is desirable to increase the storage capacity of the ROM memory cell.